1. Field of the Invention
The present invention relates to a semiconductor memory device of a clock synchronous type and, more particularly, to a technology of reducing power consumption of a system on which the semiconductor memory device is mounted.
2. Description of the Related Art
An SDRAM (Synchronous DRAM) is generally known as the semiconductor memory device of the clock synchronous type. As the SDRAM, there are an SDR (Single Data Rate) type and a DDR (Double Data Rate) type. The SDR-SDRAM accepts a command and an address in synchronization with rising edges of a clock signal CLK, and inputs/outputs data in synchronization with the rising edges of the clock signal CLK. The DDR-SDRAM accepts the command and the address in synchronization with the rising edges of the clock signal and inputs/outputs the data in synchronization with both of the rising edge and a falling edge of the clock signal CLK.
FIG. 1 shows the operation of the SDR-SDRAM. In this example, a read burst length is set as xe2x80x9c4xe2x80x9d. The read burst length is the number of outputting read data successively, in response to one read command RD.
First, an active command ACT is supplied to a bank BK0 in synchronization with the first clock signal CLK, and the bank BK0 is activated (FIG. 1(a)). Next, the active command ACT is supplied to a bank BK1 in synchronization with the second clock signal CLK, and the bank BK1 is activated (FIG. 1(b)).
The read command RD is supplied to the bank BK0 in synchronization with the third clock signal CLK. Data D0 to D3 which are read in the bank BK0 are sequentially latched by a data latch in synchronization with rising edges of an internal clock signal ICLK (FIG. 1(c)). The read data D0 to D3 which are latched by the data latch are outputted sequentially from a data input/output terminal DQ in synchronization with the next rising edges of the internal clock signal lCLK, respectively (FIG. 1(d)).
Next, the read command RD is supplied to the bank BK1 in synchronization with the eighth clock signal CLK. Data D4 to D7 which are read in the bank BK1 are sequentially latched by the data latch in synchronization with rising edges of the internal clock signal 1CLK (FIG. 1(e)). The read data which are latched by the data latch are outputted sequentially from the data input/output terminal DQ in synchronization with the next rising edges of the internal clock signal 1CLK, respectively (FIG. 1(f)).
The read command RD is supplied again to the bank BK0 in synchronization with the twelfth clock signal CLK, and, similarly to the above, the bank BK0 is operated and read data D8 to D11 are sequentially outputted from the data input/output terminal DQ in synchronization with the rising edges of the internal clock signal ICLK (FIG. 1(g)).
FIG. 2 shows the operation of the DDR-SDRAM. In this example, the read burst length is set as xe2x80x9c8xe2x80x9d. Incidentally, the DDR-SDRAM receives clock signals CLK and /CLK which are complementary to each other.
First, an active command ACT is supplied to a bank BK0 in synchronization with the first clock signal CLK, and the bank BK0 is activated (FIG. 2(a)). Next, the active command ACT is supplied to a bank BK1 in synchronization with the second clock signal CLK, and the bank BK1 is activated (FIG. 2(b)).
A read command RD is supplied to the bank BK0 in synchronization with the third clock signal CLK. Data D0 to D7 which are read in the bank BK0 are outputted to a parallel/serial conversion circuit by two bits, in synchronization with rising edges of an internal clock signal 1CLK (FIG. 2(c)). The parallel/serial conversion circuit sequentially converts the parallel read data (D0 and D1, for example) into serial data. Then, the serial read data D0 to D7 are outputted from a data input/output terminal DQ in synchronization with internal clock signals CLKEVEN and CLKODD which are complementary to each other, respectively (FIG. 2(d)). Namely, in the DDR-SDRAM, the read data D0 to D7 are sequentially outputted in synchronization with both of the rising edges and the falling edges of the clock signal CLK.
Next, the read command RD is supplied to the bank BK1 in synchronization with the eighth clock signal CLK. Data D8 to D15 which are read in the bank BK1 are outputted to the parallel/serial conversion circuit by two bits, in synchronization with the internal clock signal lCLK (FIG. 2(e)). The parallel/serial conversion circuit converts the parallel read data into the serial data. Then, the serial read data D8 to D15 are outputted from the data input/output terminal DQ, in synchronization with the internal clock signals CLKEVEN and CLKODD which are complementary to each other, respectively (FIG. 2(f)).
The read command RD is supplied again to the bank BK0 in synchronization with the twelfth clock signal CLK, and, similarly to the above, the bank BK0 is operated and read data D16 to D23 are outputted from the data input/output terminal DQ in synchronization with the clock signal CLK (FIG. 2(g)).
The above-described SDR-SDRAM and the DDR-SDRAM accept the command and the address in synchronization with the rising edges of the clock signal CLK at all times. Therefore, a control circuit and the banks BK0 and BK1 inside the SDRAM operate in synchronization with the rising edges of the clock signal CLK, and perform read operation. Further, an output of the first read data is started in synchronization with the rising edge of the clock signal CLK at all times. As to write operation, the command and the address are accepted in synchronization with the rising edges of the clock signal LCK, and reception of write data is started in synchronization with the rising edge of the clock signal CLK, similarly to the read operation.
Thus, according to the conventional SDR-SDRAM and DDR-SDRAM, the command and the address are inputted in synchronization with the rising edges of the clock signal CLK only, and the control circuit and the banks inside the SDRAM are operated at timings with reference to the rising edge of the clock signal CLK. Hence, there is no alternative but to increase a frequency of the clock signal CLK, in order to increase a reception rate of the command. However, when the frequency of the clock signal CLK is increased, the power consumption of a clock synchronization circuit of the system on which the SDRAM is mounted is increased.
Moreover, since an internal circuit of the SDRAM is operated at timing with reference to the rising edge of the clock signal CLK in the conventional art, the assumption is not made that the command and the address are accepted in synchronization with the falling edges of the clock signal CLK. Supposing that the command and the address are accepted in synchronization with the falling edges of the clock signal CLK, it is impossible to operate the internal circuit at the timing with reference to the falling edge of the clock signal CLK. Namely, there is no merit in accepting the command and the address in synchronization with the falling edges of the clock signal CLK.
It is an object of the present invention to reduce power consumption of a system on which a semiconductor memory device is mounted, without reducing the data input/output rate for the semiconductor memory device.
According to one of the aspects of the semiconductor memory device of the present invention, a command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A timing control circuit sets timing to start outputting read data and timing to start inputting write data by a data input/output circuit at either the rising edge or the falling edge of the clock signal, respectively, in response to the edge of the clock signal in receiving the command signal. The data input/output circuit starts an output of the read data and an input of the write data in synchronization with the edges (either the rising edge or the falling edge of the clock signal) set by the timing control circuit.
For example, in write operation, the timing to start inputting the write data changes in response to reception timing of a write command signal. Similarly, in read operation, the timing to start outputting the read data changes in response to reception timing of a read command signal. Thus, by changing the timing to start operation of the data input/output circuit in response to the reception timing of the command signal, the write operation and the read operation can be performed without delaying the timings the data is input and output, even when the command signal is supplied in synchronization with any edge of the clock signal. In the conventional art, for example, the read data is begun outputting in synchronization with only the rising edge of the clock signal. This applies to both of the semiconductor memory device of an SDR (Single Data Rate) type which inputs and outputs data in synchronization with one of the edges of the clock signal and the semiconductor memory device of a DDR (Double Data Rate) type which inputs and outputs data in synchronization with both edges of the clock signal.
Moreover, since the command receiver circuit can receive the command signal in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when the reception rate of the command signal is the same as that of the conventional art. As a result of this, in the system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce the power consumption of the clock synchronization circuit in the system, without reducing the data input/output rate for the semiconductor memory device.
According to another aspect of the semiconductor memory device of the present invention, the data input/output circuit includes a data output part and a data input part. The data output part outputs the read data successively for a plurality of times in synchronization with both edges of the clock signal, in response to the single command signal. The data input part inputs the write data successively for a plurality of times in synchronization with the both edges of the clock signal, in response to the single command signal. Hence, in the system on which the semiconductor memory device having a so-called burst mode function is mounted, it is possible to reduce the power consumption of the clock synchronization circuit in the system.
According to another aspect of the semiconductor memory device of the present invention, a first clock generator generates a first clock signal in synchronization with the rising edge of the clock signal. A second clock generator generates a second clock signal in synchronization with the falling edge of the clock signal. A memory control circuit starts read operation and write operation from/to a memory cell array in synchronization with either the first clock signal or the second clock signal, respectively. A clock selection circuit outputs either the first clock signal or the second clock signal to the memory control circuit, in response to the edge of the clock signal in receiving the command signal.
Thus, the timings to start operation of the read operation and the write operation are changed in response to the reception timing of the command signal so that the write operation and the read operation can be performed at optimum timings without any loss in internal operation, in any of the cases where the command signal is supplied in synchronization with any edge of the clock signal.
The operation start timing of the memory control circuit can be changed only by switching to the first clock signal or to the second clock signal in response to the reception timing of the command signal. Namely, the operation timing of the memory control circuit can be changed by the simple control.
According to another aspect of the semiconductor memory device of the present invention, the command receiver circuit receives the read command signal and the write command signal as command signal. The clock selection circuit outputs either the first clock signal or the second clock signal to the memory control circuit according to a type of the command signal. Thus, by changing the timing to start operation of the memory control circuit is according to the command signal, the clock number from the reception of the read command signal to the start of the output of the read data (read latency) and the clock number from the reception of the write command signal to the start of the input of the write data (write latency) can be freely set without restraint on each other.
According to another aspect of the semiconductor memory device of the present invention, a third clock generator generates a third clock signal whose frequency is double the frequency of the clock signal and is in synchronization with the clock signal. The command receiver circuit receives the command signal in synchronization with the third clock signal. The command receiver circuit is operated in synchronization with one of the edges of the third clock signal, and not with the rising edge or the falling edge of the clock signal, so that the command receiver circuit can be constituted simply. According to another aspect of the semiconductor memory device of the present invention, a third clock generator generates a third clock signal whose frequency is double the frequency of the clock signal and is in synchronization with the clock signal. The data input/output circuit inputs the read data and outputs the write data in synchronization with the third clock signal, respectively. The data input/output circuit is operated in synchronization with one of the edges of the third clock signal, and not with the rising or falling edges of the clock signal, so that the data input/output circuit can be constituted simply.
According to another aspect of the semiconductor memory device of the present invention, the data input/output circuit includes a parallel/serial conversion circuit for converting the parallel read data into serial data and for outputting the converted serial data in synchronization with the third clock signal. The data used inside the semiconductor memory device is in parallel and the data which is outputted to the exterior is in serial, thereby allowing the memory operation cycle to have the margin. As a result of this, it is possible to fabricate the semiconductor memory device by using an inexpensive fabrication technology, and to reduce a fabrication cost of the semiconductor memory device.
According to another aspect of the semiconductor memory device of the present invention, the memory control circuit generates a read transfer signal synchronizing with timing the read data is output from the memory cell array. The data input/output circuit receives the parallel read data in synchronization with the read transfer signal. Namely, the data input/output circuit receives the read data not in synchronization with the clock signal, but by using the read transfer signal which synchronizes with the actual read operation. Therefore, it is possible to transfer the read data to the data input/output circuit in a minimum amount of time and to perform the read operation at high speed.
According to another aspect of the semiconductor memory device of the present invention, the data input/output circuit includes a serial/parallel conversion circuit for converting the serial write data into parallel data and outputting the converted parallel data in synchronization with the third clock signal. The data which is inputted from the exterior is in serial and the data used inside the semiconductor memory device is in parallel, thereby allowing the memory operation cycle to have the margin, similar to the above. As a result of this, it is possible to fabricate the semiconductor memory device by using the inexpensive fabrication technology, and to reduce the fabrication cost of the semiconductor memory device.
According to another aspect of the semiconductor memory device of the present invention, the memory control circuit generates a write transfer signal synchronizing with timing the write data is supplied to the memory cell array. The data input/output circuit outputs the serial write data to the memory cell array in synchronization with the write transfer signal. Namely, the memory cell array receives the write data not in synchronization with the clock signal, but by using the write transfer signal which synchronizes with the actual write operation. Therefore, it is possible to supply the write data to the memory cell array in a minimum amount of time and to perform the read operation at high speed.
According to another aspect of the semiconductor memory device of the present invention, a plurality of banks each include memory cells and operate independently. The memory control circuit is respectively formed corresponding to each of the banks. The memory control circuit is formed for each bank so that the power consumption of the clock synchronization circuit in a system can be reduced, even in the system on which the semiconductor memory device having a plurality of the banks is mounted.
According to another aspect of the semiconductor memory device of the present invention, the banks are connected with the data input/output circuit by a common data bus line which is common to all of the banks, so that the wiring area of the data bus line can be minimized and the chip size of the semiconductor memory device can be reduced.
According to another aspect of the semiconductor memory device of the present invention, the banks are respectively connected with the data input/output circuit by different data bus lines, the connection being done independently from each other. Hence, it is possible to minimize a wiring length of the data bus lines and to reduce the number of transistors to be connected to the data bus lines. Therefore, it is possible to reduce power used for driving the data bus lines and to reduce the power consumption of the semiconductor memory device during operation.
According to another aspect of the semiconductor memory device of the present invention, a data strobe terminal inputs a write data strobe signal in synchronization with an external clock signal during write operation and outputs a read data strobe signal in synchronization with the external clock signal during read operation. The data input/output circuit outputs the read data in synchronization with both edges of the read data strobe signal and inputs the write data in synchronization with both edges of the write data strobe signal. Thus, even in the semiconductor memory device whose clock signal for inputting/outputting the data is a data strobe signal, it is also possible to reduce power consumption of the clock synchronization circuit in the system.